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edo (hyper page mode) 4194304-bit (262144-word by 16-bit) dynamic ram m5m44265cj,tp-5,-6,-7,-5s,-6s,-7s mitsubishi lsis 1 description features standard 40pin soj, 44 pin tsop (ii) single 5v?0% supply low stand-by power dissipation cmos input level 5.5mw (max) cmos input level 550? (max)* operating power dissipation m5m44265cxx-5,-5s 688mw (max) m5m44265cxx-6,-6s 605mw (max) m5m44265cxx-7,-7s 523mw (max) self refresh capability* self refresh current 150? (max) extended refresh capability extended refresh current 150? (max) hyper-page mode (512-column random access), read-modify- write, ras-only refresh, cas before ras refresh, hidden refresh capabilities. early-write mode, oe and w to control output buffer impedance 512 refresh cycles every 8.2ms (a 0 ~a 8 ) 512 refresh cycles every 128ms (a 0 ~a 8 )* byte or word control for read/write operation (2cas, 1w type) * : applicable to self refresh version (m5m44265cj,tp-5s,-6s,-7s : option) only xx=j,tp type name access time (max.ns) ras access time (max.ns) cas (max.ns) access time address time (min.ns) cycle dissipa- (typ.mw) power tion m5m44265cxx-7,-7s m5m44265cxx-6,-6s 60 70 15 20 30 35 110 130 550 475 15 20 access time (max.ns) oe m5m44265cxx-5,-5s 50 13 25 90 625 13 application microcomputer memory, refresh memory for crt, frame buffer memory for crt pin configuration (top view) 1 9 2 3 4 5 11 10 12 13 40 39 38 37 36 30 32 31 29 28 dq 1 a 0 a 1 a 2 a 3 (5v)v cc v ss (0v) nc a 8 a 7 a 6 a 5 a 4 w ras ucas oe outline 40p0k (400mil soj) 6 7 8 35 34 33 16 18 17 19 20 14 15 25 23 24 22 21 27 26 dq 2 dq 3 dq 4 dq 5 dq 6 dq 7 dq 8 (5v)v cc (5v)v cc nc nc lcas nc dq 12 dq 11 dq 10 dq 9 v ss (0v) dq 16 dq 15 dq 14 dq 13 v ss (0v) 1 9 2 3 4 5 13 10 14 15 44 43 42 41 40 32 36 35 31 30 dq 1 a 0 a 1 a 2 a 3 (5v)v cc v ss (0v) nc a 8 a 7 a 6 a 5 a 4 w ras ucas oe outline 44p3w-r (400mil tsop nomal bend) 6 7 8 39 38 37 18 20 19 21 22 16 17 27 25 26 24 23 29 28 dq 2 dq 3 dq4 dq 5 dq 6 dq 7 dq 8 (5v)v cc (5v)v cc nc nc lcas nc dq 12 dq 11 dq 10 dq 9 v ss (0v) dq 16 dq 15 dq 14 dq 13 v ss (0v) nc: no connection edo (hyper page mode) 4194304-bit (262144-word by 16-bit) dynamic ram m5m44265cj,tp-5,-6,-7, -5s,-6s,-7s mitsubishi lsis pin description pin name a 0 ~a 8 dq 1 ~dq 16 ras ucas w oe v cc v ss function address inputs data inputs / outputs row address strobe input upper byte control column address strobe input write control input power supply (+5v) ground (0v) output enable input lower byte control column address strobe input lcas this is a family of 262144-word by 16-bit dynamic rams with hyper page mode fuction, fabricated with the high performance cmos process, and is ideal for the buffer memory systems of personal computer graphics and hdd where high speed, low power dissipation, and low costs are essential. the use of double-layer metalization process technology and a single-transistor dynamic storage stacked capacitor cell provide high circuit density at reduced costs. multiplexed address inputs permit both a reduction in pins and an increase in system densities. self or extended refresh current is low enough for battery back-up application. this device has 2cas and 1w terminals with a refresh cycle of 512 cycles every 8.2ms.
edo (hyper page mode) 4194304-bit (262144-word by 16-bit) dynamic ram m5m44265cj,tp-5,-6,-7,-5s,-6s,-7s mitsubishi lsis 2 function in addition to hyper page mode, normal read, write and read- modify-write operations the m5m44265cj, tp provides a number of table 1 input conditions for each mode of other functions, e.g., ras-only refresh and delayed-write. the input conditions for each are shown in table 1. note : act : active, nac : nonactive, dnc : don' t care, opn : open operation lower byte read upper byte read word read lower byte write upper byte write ras only refresh self refresh* word write cas before ras (extended * ) refresh ras lcas oe inputs input/output w dq 1 ~dq 8 dq 9 ~dq 16 act act act act act act act nac act nac act act nac act nac dnc nac nac nac act act act dnc dnc act act act nac nac nac dnc dnc d out opn d out d in dnc d in opn opn opn d out d out dnc d in d in opn opn act act dnc dnc opn opn stand-by act dnc dnc opn d out ucas nac act act nac act act nac dnc act act act hidden refresh act act act act d out opn block diagram a 0 a 1 a 2 a 3 a 4 a 5 a 6 a 7 a 8 address inputs clock generator circuit column decoder sense refresh amplifier & i /o control row deco der row & colu- mn add- ress buff- er memory cell (4194304 bits) (8) upper data in buffer (8)upper data out buffer v cc (5v) v ss (0v) dq 9 oe dq 10 dq 16 upper data inputs / outputs output enable input lower byte control column address strobe input row address strobe input write control input lcas w ras a 0 ~ a 8 a 0 ~ a 8 ucas upper byte control column address strobe input (8)lower data out buffer (8)lower data in buffer lower upper dq 1 dq 2 dq 8 lower data inputs / outputs v cc (5v) v ss (0v) v cc (5v) v ss (0v) nac
edo (hyper page mode) 4194304-bit (262144-word by 16-bit) dynamic ram m5m44265cj,tp-5,-6,-7,-5s,-6s,-7s mitsubishi lsis 3 absolute maximum ratings symbol v cc v i v o i o p d t opr t stg parameter conditions ratings unit v v v ma mw -1~7 50 1000 0~70 -65~150 with respect to v ss ta=25 c supply voltage input voltage output voltage output current power dissipation operating temperature storage temperature recommended operating conditions unit limits min nom max v v v v 0 0.8 0 5.5 0 2.4 -0.5** parameter supply voltage supply voltage high-level input voltage, all inputs low-level input voltage, all inputs v cc symbol v ss v ih v il note 1 : all voltage values are with respect to v ss. 5.0 4.5 6.0 (ta=0~70?c, unless otherwise noted) (note 1) note 2: current flowing into an ic is positive, out is negative. note 3: i cc1 (av) , i cc3 (av) , i cc4 (av) , and i cc6 (av) are dependent on cycle rate. maximum current is measured at the fastest cycle rate. note 4: i cc1 (av) and i cc4 (av) are dependent on output loading. specified values are obtained with the output open. note 5: column address can be changed once or less while ras=v il and cas=v ih . electrical characteristics (ta=0~70?c, v cc =5v?0%, v ss =0v, unless otherwise noted) (note 2) symbol v oh v ol i oz i i i cc1(av) i cc2 i cc3(av) i cc4(av) i cc6(av) high-level output voltage parameter limits min max unit typ test conditions low-level output voltage off-state output current input current average supply current from vcc, operating (note 3,4,5) (note 3,5) (note 3,4,5) supply current from v cc , stand-by average supply current from vcc, ras only refresh mode average supply current from vcc hyper page mode average supply current from vcc cas before ras refresh mode m5m44265c-5,-5s m5m44265c-6,-6s m5m44265c-7,-7s i oh =-2ma i ol =2ma q floating 0v v out 5.5v 0v v in +6.0v, other inputs pins=0v ras, cas cycling t rc =t wc =min. output open ras= cas =v ih , output open ras cycling, cas=v ih t rc =min. output open ras=v il , cas cycling t pc =min. output open cas before ras refresh cycling t rc =min. output open v v ma ma ma ma ma v cc 0.4 10 10 2 1.0 115 100 85 2.4 0 -10 -10 125 110 95 (note 6) 125 110 95 125 110 95 m5m44265c-5,-5s m5m44265c-6,-6s m5m44265c-7,-7s m5m44265c-5,-5s m5m44265c-6,-6s m5m44265c-7,-7s m5m44265c-5,-5s m5m44265c-6,-6s m5m44265c-7,-7s average supply current from v cc extended-refresh mode ? 150 average supply current from v cc self-refresh mode ? 150 (note 6) ras= cas 3 v cc -0.5v output open 0.1 * ? ? i cc8(av) * i cc9(av) * * * : v il(min) is -2.0v when pulse width is less than 25ns. (pulse width is with respect to vss.) ras cycling cas 0.2v or cas before ras refresh cycling ras 0.2v or 3 v cc -0.2v cas 0.2v or 3 v cc -0.2v w 0.2v or 3 v cc -0.2v oe 0.2v or 3 v cc -0.2v a 0 ~a 8 0.2v or 3 v cc -0.2v dq=open t rc =250?, t ras =t ras min ~1? (note 3,5) (note 6) ?c ?c -1~7 -1~7 ras=cas 0.2v output open
edo (hyper page mode) 4194304-bit (262144-word by 16-bit) dynamic ram m5m44265cj,tp-5,-6,-7,-5s,-6s,-7s mitsubishi lsis 4 note 6: an initial pause of 500? is required after power-up followed by a minimum of eight initialization cycles (ras-only refresh or cas before ras refresh cycles). note the ras may be cycled during the initial pause. and 8 initialization cycles are required after prolonged periods (greater than 8.2ms) of ras inactivity before proper device operation is achieved. 7: measured with a load circuit equivalent to 1ttl and 50pf. the reference levels for measuring of output signals are 2.0v(v oh ) and 0.8v(v ol ). 8: assumes that t rcd 3 t rcd(max) and t asc 3 t asc(max) and t cp 3 t cp(max). 9: assumes that t rcd t rcd(max) and t rad t rad(max) . if t rcd or t rad is greater than the maximum recommended value shown in this table, t rac will increase by amount that t rcd exceeds the value shown. 10: assumes that t rad 3 t rad(max) and t asc t asc(max) . 11: assumes that t cp t cp(max) and t asc 3 t asc(max) . 12: t oez (max) , t wez(max) , t off(max) and t rez(max) defines the time at which the output achieves the high impedance state (i out 10? ) and is not reference to v oh(min) or v ol(max) . 13: output is disabled after both ras and cas go to high. switching characteristics (ta=0~70?c, v cc =5v?0%, v ss =0v, unless otherwise noted, see notes 6,14,15) limits min max parameter access time from cas access time from ras columu address access time symbol t cac unit min max min max ns ns ns ns ns ns 5 15 30 33 15 60 t rac t aa t cpa t oea t clz access time from cas precharge output low impedance time from cas low output disable time after cas high (note 7,8) (note 7,9) (note 7,10) (note 7,11) (note 7) 5 t off t oez (note 12) (note 7) output disable time after oe high access time from oe 15 15 5 13 25 28 13 50 13 13 ns ns 20 35 38 70 20 20 20 m5m44265c-5,-5s m5m44265c-6,-6s m5m44265c-7,-7s capacitance limits min max unit typ pf pf pf input capacitance, address inputs c i (a) c i (clk) c i / o symbol parameter test conditions input capacitance, clock inputs input/output capacitance, data ports 5 7 v i =v ss f=1mhz v i =25mvrms 7 (ta=0~70?c, v cc =5v?0%, v ss =0v, unless otherwise noted) output disable time after we high output disable time after ras high output hold time from cas output hold time from ras (note 13) t ohc t ohr t wez t rez (note 13) (note 12,13) (note 12) 15 15 13 13 ns ns 20 20 ns 5 5 5 ns 5 5 5 (note 12,13)
edo (hyper page mode) 4194304-bit (262144-word by 16-bit) dynamic ram m5m44265cj,tp-5,-6,-7,-5s,-6s,-7s mitsubishi lsis 5 read and refresh cycles note 22: either t rch or t rrh must be satisfied for a read cycle. limits min max parameter read cycle time ras low pulse width cas low pulse width symbol t rc unit min max min max ns ns ns ns ns ns t ras t cas t csh t rsh t rcs cas hold time after ras low read setup time before cas low read hold time after cas high (note 22) t rch t rrh ns ns t ral t och t orh ras hold time after cas low read hold time after ras high column address to ras hold time cas hold time after oe low ras hold time after oe low ns ns ns 10000 10000 10000 10000 10000 10000 0 0 90 50 8 40 13 0 25 13 13 0 0 110 60 10 48 15 0 30 15 15 0 0 130 70 13 55 20 0 35 20 20 (note 22) m5m44265c-5,-5s m5m44265c-6,-6s m5m44265c-7,-7s limits min max parameter refresh cycle time ras high pulse width delay time, ras low to cas low symbol t ref unit min max min max ms ns ns ns ns ns t rp t rcd t crp t rpc t cpn delay time, cas high to ras low delay time, ras high to cas low cas high pulse width (note 20) (note 16) (note 17) (note 18) ns ns ns ns ns ns t rad t asr t asc t rah t cah t t column address delay time from ras low row address setup time before ras low column address setup time before cas low row address hold time after ras low column address hold time after cas low transition time timing requirements (for read, write, read-modify-write, refresh and hyper-page mode cycles) (note 19) (note 19) delay time, data to cas low delay time, data to oe low delay time, cas high to data delay time, oe high to data t dzc t dzo t cdd t odd 42 35 0 30 13 50 20 5 13 15 10 10 0 0 1 0 0 20 38 30 13 50 32 25 0 40 10 50 18 5 8 13 8 8 0 0 1 0 50 20 5 10 15 0 0 0 13 13 10 10 0 1 0 0 15 15 ns ns ns ns note 14: the timing requirements are assumed t t =2ns. 15: v ih(min) and v il(max) are reference levels for measuring timing of input signals. 16: t rcd(max) is specified as a reference point only. if t rcd is less than t rcd(max) , access time is t rac . if t rcd is greater than t rcd(max ), access time is controlled exclusively by t cac or t aa . 17: t rad(max) is specified as a reference point only. if t rad 3 t rad(max) and t asc t asc(max ), access time is controlled exclusively by t aa . 18: t asc(max) is specified as a reference point only. if t rcd 3 t rcd(max) and t asc 3 t asc(max) , access time is controlled exclusively by t cac . 19: either t dzc or t dzo must be satisfied. 20: either t rdd or t cdd or t odd must be satisfied. 21: t t is measured between v ih(min) and v il(max) . (ta=0~70?c, v cc =5v?0%, v ss =0v, unless otherwise noted, see notes 14,15) 20 (note 20) (note 21) m5m44265c-5,-5s m5m44265c-6,-6s m5m44265c-7,-7s 8.2 8.2 8.2 ms t ref refresh cycle time * 128 128 128 (note 20) delay time, ras high to data t rdd 13 15 ns 20 t cal column address to cas hold time ns 13 18 23
edo (hyper page mode) 4194304-bit (262144-word by 16-bit) dynamic ram m5m44265cj,tp-5,-6,-7,-5s,-6s,-7s mitsubishi lsis 6 read-write and read-modify-write cycles note 23: t rwc is specified as t rwc(min) = t rac(max) + t odd(min) + t rwl(min) + t rp(min) +4 t t . 24: t wcs , t cwd , t rwd and t awd and t cpwd are specified as reference points only. if t wcs 3 t wcs(min) the cycle is an early write cycle and the dq pins will remain high impedance throughout the entire cycle. if t cwd 3 t cwd(min) , t rwd 3 t rwd(min) , t awd 3 t awd(min) and t cpwd 3 t cpwd(min) (for hyper page mode cycle only), the cycle is a read-modify-write cycle and the dq will contain the data read from the selected address. if neither of the above condition (delayed write) of the dq (at access time and until cas or oe goes back to v ih ) is indeterminate. limits min max parameter read write/read modify write cycle time ras low pulse width cas low pulse width symbol t rwc unit min max min max ns ns ns ns ns ns t ras t cas t csh t rsh t rcs cas hold time after ras low ras hold time after cas low read setup time before cas low (note 23) (note 24) ns ns ns t cwd t rwd t awd delay time, cas low to w low delay time, ras low to w low delay time, address to w low oe hold time after w low t oeh 15 13 20 ns 10000 10000 10000 10000 10000 44 89 44 82 0 32 77 47 133 38 38 0 28 65 40 109 75 70 57 107 57 99 0 42 92 57 161 (note 24) (note 24) m5m44265c-5,-5s m5m44265c-6,-6s m5m44265c-7,-7s write cycle (early write and delayed write) limits min max parameter write cycle time ras low pulse width cas low pulse width symbol t wc unit min max min max ns ns ns ns ns ns t ras t cas t csh t rsh t wcs cas hold time after ras low write setup time before cas low write hold time after cas low (note 24) t wch t cwl ns ns t rwl t wp t ds ras hold time after cas low cas hold time after w low ns ns ns 10000 10000 10000 10000 10000 10000 ns 8 0 90 50 8 40 13 8 8 8 0 8 10 0 110 60 10 48 15 10 10 10 0 10 t dh ras hold time after w low data setup time before cas low or w low data hold time after cas low or w low write pulse width 13 0 130 70 13 55 20 13 13 0 13 13 m5m44265c-5,-5s m5m44265c-6,-6s m5m44265c-7,-7s 10000
edo (hyper page mode) 4194304-bit (262144-word by 16-bit) dynamic ram m5m44265cj,tp-5,-6,-7,-5s,-6s,-7s mitsubishi lsis 7 limits min parameter symbol unit min max min max ns ns ns ns ns ns (note 27) (note 28) (note 24) 28 20 65 5 28 57 16 100000 13 30 92 38 79 10 25 77 33 66 m5m44265c-5,-5s m5m44265c-6,-6s m5m44265c-7,-7s 16 100000 max 13 100000 cas before ras refresh cycle (note 29) limits min max parameter cas setup time before ras low symbol t csr unit min max min max ns ns t chr 5 10 cas hold time after ras low 5 10 5 15 note 29: eight or more cas before ras cycles instead of eight ras cycles are necessary for proper operation of cas before ras refresh mode. m5m44265c-5,-5s m5m44265c-6,-6s m5m44265c-7,-7s ns 17 17 22 t cas cas low pulse width cbr self refresh ras low pulse width t rass ? t rps t chs 100 100 110 -50 100 90 -50 130 -50 cbr self refresh ras high precharge time cbr self refresh cas hold time self refresh cycle * (note 30) limits min max parameter symbol unit min max min max ns ns m5m44265c-5,-5s m5m44265c-6,-6s m5m44265c-7,-7s note 25: all previously specified timing requirements and switching characteristics are applicable to their respective hyper page mode cycle. 26: t hpc(min) is specified in the case of read-only and early write-only in hyper page mode. 27: t ras(min) is specified as two cycles of cas input are performed. 28: t cp(max) is specified as a reference point only. hyper page mode read/write cycle time ras low pulse width for read or write cycle cas high pulse width ras hold time after cas precharge delay time, cas precharge to w low hyper page mode read write / read modify write cycle time hold time to maintain the data hi-z until cas access oe pulse width (hi-z control) w pulse width (hi-z control) output hold time from cas low delay time, cas low to w low after read delay time, address to w low after read delay time, cas precharge to w low after read delay time, cas low to oe high after read delay time, address to oe high after read delay time, cas precharge to oe high after read t hpc t hprwc t doh t ras t cp t cprh t cpwd t chol t oepe t wpe t hcwd t hawd t hpwd t hcod t haod t hpod (note 26) hyper page mode cycle (read, early write, read-write, read-modify-write cycle, read write mix cycle, hi-z control by oe or w) (note 25) ns ns ns ns ns ns ns ns ns ns 28 43 7 7 40 7 42 60 57 32 50 47 43 25 8 13 60 35 38 20 50 30 33 15 5 5 7 7 7 7 7 7
edo (hyper page mode) 4194304-bit (262144-word by 16-bit) dynamic ram m5m44265cj,tp-5,-6,-7,-5s,-6s,-7s mitsubishi lsis 8 timing diagrams (note 31) read cycle t crp t asr t rah t rad t rcd t csh t asc t cah t rcs t ras t rc t rsh t cas t ral t aa t clz t rac t off t rch t rp hi-z note 31 indicates the don't care input. v ih(min) v in v ih(max) or v il(min) v in v il(max) indicates the invalid output. t dzc t oez t oea t och t dzo t cdd t orh t rpc t crp lcas/ucas dq 1 ~dq 16 (inputs) ras w dq 1 ~dq 16 (outputs) oe a 0 ~a 8 v ih v il v oh v ol v ih v il v ih v il v ih v il v ih v il v ih v il row address column address hi-z hi-z t cac t oea data valid t odd t ohr t ohc t wez t rez t rrh t asr t cal row address
edo (hyper page mode) 4194304-bit (262144-word by 16-bit) dynamic ram m5m44265cj,tp-5,-6,-7,-5s,-6s,-7s mitsubishi lsis byte read cycle t crp t asr t rah t rad t rcd t csh t asc t cah t rcs t ras t rc t rsh t cas t ral t rac t rch t asr t rp hi-z t odd t oea t och t dzo t orh t cac t aa t clz t off hi-z hi-z t dzc hi-z 9 t rpc t crp t cpn ucas (or lcas) dq 1 ~dq 8 (or dq 9 ~dq 16 ) (inputs) lcas (or ucas) dq 1 ~dq 8 (or dq 9 ~dq 16 ) (outputs) dq 9 ~dq 16 (or dq 1 ~dq 8 ) (inputs) dq 9 ~dq 16 (or dq 1 ~dq 8 ) (outputs) ras w oe a 0 ~a 8 v ih v il v oh v ol v ih v il v ih v il v ih v il v ih v il v ih v il v ih v il v ih v il v oh v ol row address data valid column address t cdd t rrh t cal t oez t rez t ohr t ohc t wez row address
edo (hyper page mode) 4194304-bit (262144-word by 16-bit) dynamic ram m5m44265cj,tp-5,-6,-7,-5s,-6s,-7s mitsubishi lsis early write cycle t crp t asr t rah t rcd t csh t asc t cah t wcs t ras t wc t rsh t cas t wch t asr t rp hi-z column address row address data valid t ds t dh 10 t rpc t crp lcas/ucas dq 1 ~dq 16 (inputs) ras w dq 1 ~dq 16 (outputs) oe a 0 ~a 8 v ih v il v oh v ol v ih v il v ih v il v ih v il v ih v il v ih v il row address
edo (hyper page mode) 4194304-bit (262144-word by 16-bit) dynamic ram m5m44265cj,tp-5,-6,-7,-5s,-6s,-7s mitsubishi lsis byte early write cycle t crp t asr t rah t rcd t csh t asc t cah t wcs t ras t wc t rsh t cas t wch t asr t rp hi-z column address row address data valid t ds t dh hi-z 11 t rpc t crp ucas (or lcas) dq 1 ~dq 8 (or dq 9 ~dq 16 ) (inputs) lcas (or ucas) dq 1 ~dq 8 (or dq 9 ~dq 16 ) (outputs) dq 9 ~dq 16 (or dq 1 ~dq 8 ) (inputs) dq 9 ~dq 16 (or dq 1 ~dq 8 ) (outputs) ras w oe a 0 ~a 8 v ih v il v oh v ol v ih v il v ih v il v ih v il v ih v il v ih v il v ih v il v ih v il v oh v ol row address
edo (hyper page mode) 4194304-bit (262144-word by 16-bit) dynamic ram m5m44265cj,tp-5,-6,-7,-5s,-6s,-7s mitsubishi lsis delayed write cycle t crp t asr t rah t rcd t csh t asc t cah t rcs t ras t wc t rsh t cas t asr t rp hi-z row address data valid column address t clz t wch t cwl t rwl t dh t ds hi-z hi-z t wp t dzc t oez t dzo t odd t oeh 12 t rpc t crp lcas/ucas dq 1 ~dq 16 (inputs) ras w dq 1 ~dq 16 (outputs) oe a 0 ~a 8 v ih v il v oh v ol v ih v il v ih v il v ih v il v ih v il v ih v il row address
edo (hyper page mode) 4194304-bit (262144-word by 16-bit) dynamic ram m5m44265cj,tp-5,-6,-7,-5s,-6s,-7s mitsubishi lsis byte delayed write cycle t crp t asr t rah t rcd t csh t asc t cah t rcs t ras t wc t rsh t cas t asr t rp hi-z column address row address data valid t clz t wch t cwl t rwl t dh t ds hi-z hi-z t dzc t oez t dzo t odd t oeh hi-z 13 t rpc t crp ucas (or lcas) dq 1 ~dq 8 (or dq 9 ~dq 16 ) (inputs) lcas (or ucas) dq 1 ~dq 8 (or dq 9 ~dq 16 ) (outputs) dq 9 ~dq 16 (or dq 1 ~dq 8 ) (inputs) dq 9 ~dq 16 (or dq 1 ~dq 8 ) (outputs) ras w oe a 0 ~a 8 v ih v il v oh v ol v ih v il v ih v il v ih v il v ih v il v ih v il v ih v il v ih v il v oh v ol t wp row address
edo (hyper page mode) 4194304-bit (262144-word by 16-bit) dynamic ram m5m44265cj,tp-5,-6,-7,-5s,-6s,-7s mitsubishi lsis read-write, read-modify-write cycle t crp t asr t rah t rcd t csh t asc t cah t rcs t ras t rwc t rsh t cas t asr t rp hi-z column address row address data valid t clz t cwl t rwl t dh t ds hi-z hi-z t wp t dzc t oez t dzo t odd t oeh t awd t cwd t rwd data valid t aa t cac t rac t oea t rad 14 t rpc t crp lcas/ucas dq 1 ~dq 16 (inputs) ras w dq 1 ~dq 16 (outputs) oe a 0 ~a 8 v ih v il v oh v ol v ih v il v ih v il v ih v il v ih v il v ih v il row address
edo (hyper page mode) 4194304-bit (262144-word by 16-bit) dynamic ram m5m44265cj,tp-5,-6,-7,-5s,-6s,-7s mitsubishi lsis byte read-write, read-modify-write cycle t crp t asr t rah t rcd t csh t asc t cah t rcs t ras t rwc t rsh t cas t asr t rp hi-z column address row address data valid t clz t cwl t rwl t dh t ds hi-z hi-z t wp t dzc t oez t dzo t odd t oeh t awd t cwd t rwd data valid t aa t cac t rac t oea t rad hi-z 15 t rpc t crp ucas (or lcas) dq 1 ~dq 8 (or dq 9 ~dq 16 ) (inputs) lcas (or ucas) dq 1 ~dq 8 (or dq 9 ~dq 16 ) (outputs) dq 9 ~dq 16 (or dq 1 ~dq 8 ) (inputs) dq 9 ~dq 16 (or dq 1 ~dq 8 ) (outputs) ras w oe a 0 ~a 8 v ih v il v oh v ol v ih v il v ih v il v ih v il v ih v il v ih v il v ih v il v ih v il v oh v ol row address
edo (hyper page mode) 4194304-bit (262144-word by 16-bit) dynamic ram m5m44265cj,tp-5,-6,-7,-5s,-6s,-7s mitsubishi lsis 16 lcas/ucas dq 1 ~dq 16 (inputs) ras dq 1 ~dq 16 (outputs) oe a 0 ~a 8 v ih v il v oh v ol v ih v il w v ih v il v ih v il v ih v il v ih v il hyper page mode read cycle t crp t asr t rah t rad t rcd t cah t ras t cp t cac t aa t rac t asr hi-z column-1 row address t rp t cas t asc t rcs hi-z t dzc t dzo t oea t och data valid-1 t csh t hpc t cas t cp t cas t rsh column-2 column-3 t cah t asc t cah t asc t cprh t ral t rch t rrh t cdd t cpa t oez t odd t rez t off t clz t doh t rdd t cac t aa data valid-2 t cpa t doh t cac data valid-3 t aa t cal t cal t cal t ohc t ohr t wez row address
edo (hyper page mode) 4194304-bit (262144-word by 16-bit) dynamic ram m5m44265cj,tp-5,-6,-7,-5s,-6s,-7s mitsubishi lsis 17 ucas (or lcas) dq 1 ~dq 8 (or dq 9 ~dq 16 ) (inputs) lcas (or ucas) dq 1 ~dq 8 (or dq 9 ~dq 16 ) (outputs) dq 9 ~dq 16 (or dq 1 ~dq 8 ) (inputs) dq 9 ~dq 16 (or dq 1 ~dq 8 ) (outputs) ras oe a 0 ~a 8 v ih v il v oh v ol v ih v il v ih v il v ih v il v ih v il v ih v il v ih v il v oh v ol hyper page mode byte read cycle t cas t asr t rah t rad t cah t asr address column-1 row address row t asc t rcs column-3 t cah t asc t cah t asc t cprh t ral t rch t rrh t crp t rcd t ras t cp t rp t cas t csh t hpc t cp t cas t rsh t cal t cal t cal t cac t aa t rac hi-z hi-z t dzc t dzo t oea t och data valid-1 t odd t rez t off t clz t rdd t cpa t doh t cac data valid-3 t aa t ohc t ohr t dzc hi-z t cac t aa t cpa data valid-2 t clz hi-z t cdd t oez t wez t crp column-2 w v ih v il
edo (hyper page mode) 4194304-bit (262144-word by 16-bit) dynamic ram m5m44265cj,tp-5,-6,-7,-5s,-6s,-7s mitsubishi lsis 18 lcas/ucas dq 1 ~dq 16 (inputs) ras w dq 1 ~dq 16 (outputs) oe a 0 ~a 8 v ih v il v oh v ol v ih v il v ih v il v ih v il v ih v il v ih v il hyper page mode early write cycle t crp t asr t rah t rcd t cah t ras t cp t asr column-1 row address t rp t cas t asc t wcs t csh t hpc t cas t cp t cas t rsh column-2 column-3 t cah t cah t asc t asc hi-z t wch t wcs t wch t wcs t wch data valid-1 data valid-2 data valid-3 t ds t dh t ds t dh t ds t dh t cal t cal t crp row address
edo (hyper page mode) 4194304-bit (262144-word by 16-bit) dynamic ram m5m44265cj,tp-5,-6,-7,-5s,-6s,-7s mitsubishi lsis 19 t crp t rcd t ras t cp hi-z t rp t cas t csh t hpc t cas t cp t cas t rsh row address t cah data valid-2 t ds t dh t ds t dh t ds t dh t wcs t wch t wch t wcs t wcs t wch row address hyper page mode byte early write cycle column-1 column-2 column-3 t cal t asr t rah t cah t asr t asc t cah t asc t asc t cal t crp ucas (or lcas) dq 1 ~dq 8 (or dq 9 ~dq 16 ) (inputs) lcas (or ucas) dq 1 ~dq 8 (or dq 9 ~dq 16 ) (outputs) dq 9 ~dq 16 (or dq 1 ~dq 8 ) (inputs) dq 9 ~dq 16 (or dq 1 ~dq 8 ) (outputs) ras w oe a 0 ~a 8 v ih v il v oh v ol v ih v il v ih v il v ih v il v ih v il v ih v il v ih v il v ih v il v oh v ol data valid-1 data valid-3 hi-z
edo (hyper page mode) 4194304-bit (262144-word by 16-bit) dynamic ram m5m44265cj,tp-5,-6,-7,-5s,-6s,-7s mitsubishi lsis 20 hyper page mode read-write, read-modify-write cycle lcas/ucas dq 1 ~dq 16 (inputs) ras w dq 1 ~dq 16 (outputs) oe a 0 ~a 8 v ih v il v oh v ol v ih v il v ih v il v ih v il v ih v il v ih v il t asr t rah t rcd t cah t cp t asr t cas t asc t hprwc t cas address row address row t cah t asc t rwd t cwl t wp t wp t cwl t cpwd t rad t cwd t awd t awd t cwd column-1 column-2 t crp t ras t rp t csh t rwl t rcs t rcs hi-z t ds hi-z hi-z t ds data valid-2 t dh hi-z hi-z t clz t dzo t oez t odd t dzo t oez t oeh t cac data valid-1 t aa t cac data valid-2 t rac t oea t cpa t oea t odd t dzc t dh t dzc t aa t crp data valid-1 t clz
edo (hyper page mode) 4194304-bit (262144-word by 16-bit) dynamic ram m5m44265cj,tp-5,-6,-7,-5s,-6s,-7s mitsubishi lsis 21 hyper page mode byte read-write, read-modify-write cycle ucas (or lcas) dq 1 ~dq 8 (or dq 9 ~dq 16 ) (inputs) lcas (or ucas) dq 1 ~dq 8 (or dq 9 ~dq 16 ) (outputs) dq 9 ~dq 16 (or dq 1 ~dq 8 ) (inputs) dq 9 ~dq 16 (or dq 1 ~dq 8 ) (outputs) ras w oe a 0 ~a 8 v ih v il v oh v ol v ih v il v ih v il v ih v il v ih v il v ih v il v ih v il v ih v il v oh v ol t crp t asr t rah t rcd t cah t ras t cp t asr hi-z t rp t cas t asc t csh t hprwc t cas t rwl address row address row t cah t asc t rwd data valid-1 t ds t cwl t wp t wp t cwl hi-z hi-z t ds t cpwd data valid-2 t dh hi-z hi-z t clz t dzo t oez t odd t dzo t oez t oeh t rad t cwd t awd t awd t cwd t cac data valid-1 t aa t cac data valid-2 t rac t oea t cpa t oea t odd hi-z t dzc column-1 column-2 t rcs t rcs t dh t dzc t aa t crp t clz
edo (hyper page mode) 4194304-bit (262144-word by 16-bit) dynamic ram m5m44265cj,tp-5,-6,-7,-5s,-6s,-7s mitsubishi lsis 22 lcas/ucas dq 1 ~dq 16 (inputs) ras w dq 1 ~dq 16 (outputs) oe a 0 ~a 8 v ih v il v oh v ol v ih v il v ih v il v ih v il v ih v il v ih v il t crp t asr t rah t rcd t cah t ras t cp t asr hi-z t rp t cas t asc t csh t hprwc t cas t rwl t cah t asc t dzc t ds t cwl t wp t wez t dh t ds t cwd t dh t clz t dzo t oez t odd t dzo t oez t oeh t rad t awd t cpwd t cac t cac data valid-3 t clz t rac t oea t cpa t oea t wch hyper page mode mix cycle (1) t aa t cp data valid-1 t hpc t cah t asc t wcs t cal t crp row address column-3 t cas t cal data valid-2 t och t odd t rcs t dzc t aa data valid-3 column-1 column-2 row address
edo (hyper page mode) 4194304-bit (262144-word by 16-bit) dynamic ram m5m44265cj,tp-5,-6,-7,-5s,-6s,-7s mitsubishi lsis 23 lcas/ucas dq 1 ~dq 16 (inputs) ras w dq 1 ~dq 16 (outputs) oe a 0 ~a 8 v ih v il v oh v ol v ih v il v ih v il v ih v il v ih v il v ih v il data valid-1 t cah t asc data valid-3 t aa t cac t oez t ds t odd data valid-2 hi-z t dh t dzc hi-z column-1 t cah t asc t cah t asc column-2 column-3 t cpa t aa t wch t cac t oea t clz hi-z t cpa t cal t cp t cas t rch t wcs t wez t cal hyper page mode mix cycle (2) t dzc t cas t hcod t haod t hpod t hcwd t hawd t hpwd
edo (hyper page mode) 4194304-bit (262144-word by 16-bit) dynamic ram m5m44265cj,tp-5,-6,-7,-5s,-6s,-7s mitsubishi lsis 24 t crp t asr t rah t rcd t cah t ras t cp t rp t cas t csh t cas t rsh t cah t asc lcas/ucas dq 1 ~dq 16 (inputs) ras w dq 1 ~dq 16 (outputs) oe a 0 ~a 8 v ih v il v oh v ol v ih v il v ih v il v ih v il v ih v il v ih v il hyper page mode read cycle (hi-z control by oe) t rad t cac t aa t rac t asr hi-z column-1 row address t rcs hi-z t dzc t dzo t oea data valid-1 t hpc column-2 column-3 t cprh t ral t rch t rrh t cdd t cpa t oez t odd t rez t off t clz t doh t rdd t cac t aa data valid-2 t cpa t oez t cac data valid-3 t aa t clz hi-z t oepe t chol t oepe t oez t oea t och data valid-1 t ohr t ohc t crp t wez t cp t cas t cah t asc t asc row address
edo (hyper page mode) 4194304-bit (262144-word by 16-bit) dynamic ram m5m44265cj,tp-5,-6,-7,-5s,-6s,-7s mitsubishi lsis 25 t crp t asr t rah t rcd t cah t ras t cp t rp t cas t csh t cas t rsh t cah t asc lcas/ucas dq 1 ~dq 16 (inputs) ras w dq 1 ~dq 16 (outputs) oe a 0 ~a 8 v ih v il v oh v ol v ih v il v ih v il v ih v il v ih v il v ih v il hyper page mode read cycle (hi-z control by w) t rad t cac t aa t rac t asr hi-z column-1 row address t rcs hi-z t dzc t dzo t oea data valid-1 t hpc column-2 column-3 t cprh t ral t rch t rrh t cdd t cpa t oez t odd t rez t off t clz t doh t rdd t cac t aa data valid-2 t cpa t cac data valid-3 t aa t clz hi-z t och t ohr t ohc t crp t wez t cp t cas t cah t asc t asc row address t wez t wpe t rcs t rch
edo (hyper page mode) 4194304-bit (262144-word by 16-bit) dynamic ram m5m44265cj,tp-5,-6,-7,-5s,-6s,-7s mitsubishi lsis 26 ras-only refresh cycle t crp t asr t rah t ras t rc t asr t crp t rpc t rp row address hi-z row address lcas/ucas dq 1 ~dq 16 (inputs) ras w dq 1 ~dq 16 (outputs) oe a 0 ~ a 8 v ih v il v oh v ol v ih v il v ih v il v ih v il v ih v il v ih v il
edo (hyper page mode) 4194304-bit (262144-word by 16-bit) dynamic ram m5m44265cj,tp-5,-6,-7,-5s,-6s,-7s mitsubishi lsis 27 cas before ras refresh cycle, extended refresh cycle * t ras t rc t asr t crp t rpc t rp row address t rpc t rc t ras t csr t chr t csr t rpc t cpn t rcs t off hi-z t oez t rp t chr lcas/ucas dq 1 ~dq 16 (inputs) ras w dq 1 ~dq 16 (outputs) oe a 0 ~a 8 v ih v il v oh v ol v ih v il v ih v il v ih v il v ih v il v ih v il t rrh t rch t ohc t ohr t rez column address
edo (hyper page mode) 4194304-bit (262144-word by 16-bit) dynamic ram m5m44265cj,tp-5,-6,-7,-5s,-6s,-7s mitsubishi lsis hidden refresh cycle (read) (note 32) note 32: early write, delayed write, read write or read modify write cycle is applicable instead of read cycle. timing requirements and output state are the same as that of each cycle shown above. t crp t asr t rah t rad t rcd t cah t rcs t ras t rc t chr t cac t aa t clz t rac t rrh t asr t rp hi-z column address row address data valid t ras t rc t rp t rsh t asc t ral hi-z t dzc t cdd hi-z t dzo t oea t orh t odd t oez row address 28 lcas/ucas dq 1 ~dq 16 (inputs) ras w dq 1 ~dq 16 (outputs) oe a 0 ~a 8 v ih v il v oh v ol v ih v il v ih v il v ih v il v ih v il v ih v il t off t ohc t rez t rdd t ohr
edo (hyper page mode) 4194304-bit (262144-word by 16-bit) dynamic ram m5m44265cj,tp-5,-6,-7,-5s,-6s,-7s mitsubishi lsis self refresh cycle * (note 30) t rpc t rps t asr t crp row address t rass t csr t cpn t rch t rcs t rez hi-z t oez t rp t chs t rpc hi-z t rdd t odd lcas/ucas dq 1 ~dq 16 (inputs) ras w dq 1 ~dq 16 (outputs) oe a 0 ~a 8 v ih v il v oh v ol v ih v il v ih v il v ih v il v ih v il v ih v il 29 t rrh t cdd t ohr t off t ohc
edo (hyper page mode) 4194304-bit (262144-word by 16-bit) dynamic ram m5m44265cj,tp-5,-6,-7,-5s,-6s,-7s mitsubishi lsis switching from read/write operation to self refresh operation. the time interval from the falling edge of ras signal in the last cbr refresh cycle during read/write operation period to the falling edge of ras signal at the start of self refresh operation should be set within t nsd (shown in table 2). note 30 : self refresh sequence two refreshing methods should be used properly depending on the low pulse width (t rass ) of ras signal during self refresh period. 1. distributed refresh during read/write operation (a) timing diagram read / write cycle self refresh cycle read / write cycle t nsd t rass 3 100 s t snd last refresh cycle first refresh cycle table 2 definition of cbr distributed refresh (including extended refresh) switching from self refresh operation to read/write operation. the time interval from the rising edge of ras signal at the end of self refresh operation to the falling edge of ras signal in the first cbr refresh cycle during read/write operation period should be set within t snd (shown in table 2). switching from read/write operation to self refresh operation. the time interval t nsd from the falling edge of ras signal in the last ras only refresh cycle during read/write operation period to the falling edge of ras signal at the start of self refresh operation should be set within 16?. switching from self refresh operation to read/write operation. the time interval t snd from the rising edge of ras signal at the end of self refresh operation to the falling edge of ras signal in the first cbr refresh cycle during read/write operation period should be set within 16?. ras read / write cycle cbr distributed refresh ras only distributed refresh self refresh read / write t nsd 16? t snd 16? (b) definition of distributed refresh t ref t ref / 512 refresh cycle read/write cycles ras t ref / 512 read/write cycles refresh cycle refresh cycle note: hidden refresh may be used instead of cbr refresh. ras/cas refresh may be used instead of ras only refresh. 30 1.1 cbr distributed refresh 1.2 ras only distributed refresh the cbr distributed refresh performs more than 512 constant period (250? max.) cbr cycles within 128 ms. all combinations of nine row address signals (a 0 ~a 8 ) are selected during 512 constant period (16? max.) ras only refresh cycles within 8.2 ms. definition of ras only distributed refresh t nsd 250? t snd 250? read / write self refresh
edo (hyper page mode) 4194304-bit (262144-word by 16-bit) dynamic ram m5m44265cj,tp-5,-6,-7,-5s,-6s,-7s mitsubishi lsis 2. burst refresh during read/write operation (a) timing diagram read / write self refresh read / write t nsb t rass 3 100 s t snb last refresh cycles first refresh cycles table 3 read / write cycle cbr burst refresh ras only burst refresh read / write self refresh self refresh read / write t nsb +t snb 8.2ms definition of cbr burst refresh switching from read/write operation to self refresh operation. the time interval t nsb from the falling edge of ras signal in the first cbr refresh cycle during read/write operation period to the falling edge of ras signal at the start of self refresh operation should be set within 8.2 ms. switching from self refresh operation to read/write operation. the time interval t snb from the rising edge of ras signal at the end of self refresh operation to the falling edge of ras signal in the last cbr refresh cycle during read/write operation period should be set within 8.2 ms. switching from read/write operation to self refresh operation. the time interval from the falling edge of ras signal in the first ras only refresh cycle during read/write operation period to the falling edge of ras signal at the start of self refresh operation should be set within t nsb (shown in table 3). switching from self refresh operation to read/write operation. the time interval from the rising edge of ras signal at the end of self refresh operation to the falling edge of ras signal in the last ras only refresh cycle during read/write operation period should be set within t snb (shown in table 3). ras refresh cycles 511 cycles refresh cycles 511 cycles (b) definition of burst refresh 8.2ms read/write cycles ras refresh cycles 512 cycles 2.2 ras only burst refresh 2.1 cbr burst refresh the cbr burst refresh performs more than 512 continuous cbr cycles within 8.2 ms. all combination of nine row address signals (a 0 ~a 8 ) are selected during 512 continuous ras only refresh cycles within 8.2 ms. definition of ras only burst refresh 31 t snb 8.2ms t nsb 8.2ms

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